Flip Flops and Sequential Logic
August 9, 2013
We have looked at logic gates so far; the output from these is wholly dependent on the input at a particular time. With sequential circuits, the output is determined by the order in which operations are applied.
Set-Reset Flip Flop
This circuit is formed from basic combination circuits by applying a form of feedback. When the input state changes, the outputs are modified by the feedback, therefore making the output sequential.
A Set-Reset or RS Flip Flop can be created by cross coupling two NOR gates:
If Q = Off, the structure will hold its state as long as R = S = Off
Given Q is Off,
- If S and R are both Off, Q stays Off
- If S is On, and R is Off, Q changed to be On
- If S is Off and R is On, Q stays at Off
- If both S and R are On, we get an indeterminate state (more on this later)
Given Q is On,
- If S and R are both Off, Q stays On
- If S is On, and R is Off, Q stays On
- If S is Off and R is On, Q changes to be Off
- If both S and R are On, we get an indeterminate state (again, more on this later)
So, whenever S is On and R is Off, Q becomes On. Whenever S is Off and R is On, Q becomes Off.
The normal logic symbol for an S-R Flip Flop is:
Clocked S-R Flip Flop
We can ensure that the flip flop only changes state on a clock pulse by ANDing that clock pulse with the S and R inputs.
When the clock is On, the AND gates are enabled. This condition of R and S are then passed through to the flip flop. The addition of a clock input allows the data to be synchronised with the rising edge of the clock waveform.
JK Flip Flop
With SR Flip Flops the condition can exist where both S and R can simultaneously be a logical On. This leads to instability in the output such that the output state cannot be predicted.
If we restrict the inputs to the flip flop such that S and R cannot be On at the same time, then we create another type of flip flop, known as the JK Flip Flop where J = Jam and K = Kill (or Clear)
In the situation where both J and K are On, the value of Q will toggle, moving to On if it is Off and Off if it is On.
The standard symbol for this kind of flip flop is:
Trigger Flip Flop
The trigger flip flop is a restricted version of the JK Flip Flop. In this situation, both J and K are set permanently On. In this situation, Q toggles state at the end of each On pulse from the clock. Q therefore contains half the cycles of the clock, and the Q will oscillate at half the speed - it will divide by two.
JK Flip Flop Binary Counter
We're going to use four JK Flip Flops and a 555 timer to build a circuit that counts in binary. We're using the 74LS76 chip, which has the following pinout, and we'll need two of them.
Note that each chip contains two JK Flip Flops - denoted by the 1 and 2 prefix on the pinout. We actually need to use the trigger flip flop, so tie the Preset (PRE), Clear (CLR), J and K inputs of each flip flop to +5v via a 1k resistor.
Then, supply the clock from the 555 timer into the clock (1 CLK) input of the first flip flop. Then, take the output (1 Q) and pass that into the clock for the second flip flop (2 CLK). Do the same with the other two, so 2 Q goes to 1 CLK on the second chip, and 1Q on that chip goes to 2 CLK.
If you measure the pulses on the four Q outputs, you'll see that each divides the previous by two, and you end up with a standard binary progression from 0000 to 1111. See the example at http://www.wisc-online.com/Objects/ViewObject.aspx?ID=DIG4203 for a worked example.
Troubleshooting
When I breadboarded this I had trouble. The seconds 74LS76 in the chain wasn't behaving itself, it seemed to pick up the second binary digit and both 1 Q and 2 Q gave the same output. I added a 0.1uF capacitor between ground and +5v near this chip and it then began to behave itself.
